![[VerilogHDL] Project : Intelligent Vehicle Control System PPT & PDF](https://img1.daumcdn.net/thumb/R750x0/?scode=mtistory2&fname=https%3A%2F%2Fblog.kakaocdn.net%2Fdn%2FbHLRRD%2FbtsIpYsl5f8%2FAE8H7ifkwepCHb3Qk2RBeK%2Fimg.png)
Project : Intelligent Vehicle Control System ⦁ 개요 : Microblaze Soft Process Core CPU(RISC Architecture)를 이용하여 AXI4-Lite Protocol기반 각종 Peripherals 설계 및 UVM 검증을 통한 Intelligent Vehicle Control System 개발 ⦁ 기능 1. Microblaze Soft Process Core CPU & AXI4-Lite Protocol 2. Peripherals 설계 및 UVM 검증 1) UART 2) GPIO 3) FND Controller 4) UART 5) PWM ..
![[VerilogHDL] Project : Design RISC-V CPU with AHB-Lite & Peripherals PPT & PDF](https://img1.daumcdn.net/thumb/R750x0/?scode=mtistory2&fname=https%3A%2F%2Fblog.kakaocdn.net%2Fdn%2FCtbhs%2FbtsHYazJdno%2Fk6fldhl9O6Vm5kdnyulqz1%2Fimg.png)
Project : Design RISC-V CPU with AHB-Lite & Peripherals ⦁ 개요 : RISC-V RV32I Architecture CPU & AMBA AHB-Lite & Peripherals 설계 및 검증 ⦁ 기능 1. RISC-V RV32I Architecture CPU Core 1) Control Unit, Data Path 2) Single Cycle, Multi Cycle 2. AMBA Simple Bus(AHB Lite) 1) BUS Interconnector 3. Peripherals 1) RAM & ROM 2) GPI 3) GPIO ..
![[VerilogHDL] Project : FPGA Multi Function Clock PPT & PDF](https://img1.daumcdn.net/thumb/R750x0/?scode=mtistory2&fname=https%3A%2F%2Fblog.kakaocdn.net%2Fdn%2FbpE1f1%2FbtsHZujurjr%2F9nhtZ40q9LvcFIk1Vv6ViK%2Fimg.jpg)
Project : FPGA Multi Function Clock ⦁ 개요 : Digilent Basys3를 이용한 FPGA Multi Function Clock 설계 및 검증 ⦁ 기능 1. Clock ↔ Stopwatch 모드 변경 1) 스위치 조작 2) UART 조작 : "Clock" 혹은 "Stopwatch" 입력 2. Clock 모드 : FND 시간 표시 1) 스위치 & 버튼 조작 a) 스위치 : [시 : 분] 혹은 [초 : 밀리초] FND 출력 모드 선택 b) 버튼 : 시간을 설정 & 0으로 설정 2) UART 조작 a) "..