1.  Half Adder S = A’B + AB’ (XOR Gate)C = AB (AND Gate)module HalfAdder( // Port list input a, input b, output Sum, output Carry ); // Design Circuit assign Sum = a ^ b; assign Carry = a & b;endmodule  Simualtionmodule tb_HalfAdder(); reg a; reg b; wire Sum; wire Carry; HalfAdder test_HA( .a(a), .b(b), .Sum(Sum), ...

1. XOR Gate ⦁ Truth Table VINA VINB VOUT 0 0 0 0 1 1 1 0 1 1 1 0 X = A ⊕ B = A’B + B’A ⇒ Input 2개가 서로 다를 때 1 출력 → 덧셈과 유사 (1) Logic Level Design → TR 22개 (2) Switch Level Design → TR 6개 2. Adder Half Adder(carry X) : 17 + 15 = 2 Full Adder(carry O) : 17 + 15 = 32 3. Half Adder : 덧셈 연산을 수행하는 디지털 회로 Truth Table VINA VINB S(out) C(out) 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 S = A’B + AB’ (XOR Gate) C = AB ..