[VerilogHDL] HalfAdder, FullAdder, 4bit Adder

1.  Half Adder

 

• S = A’B + AB’ (XOR Gate)
• C = AB (AND Gate)

module HalfAdder(       // Port list
    input a,
    input b,
    output Sum,
    output Carry
    );
    
    // Design Circuit
    assign Sum = a ^ b;
    assign Carry = a & b;
endmodule

RTL Schematic

 

 

Simualtion

module tb_HalfAdder();

    reg a;
    reg b;
    wire Sum;
    wire Carry;
    
    HalfAdder test_HA(
        .a(a),
        .b(b),
        .Sum(Sum),
        .Carry(Carry)
    );
    
    initial begin
        #00 a = 0; b = 0;
        #10 a = 0; b = 1;
        #10 a = 1; b = 0;
        #10 a = 1; b = 1;
        #10 $finish;
     end

endmodule

module HalfAdder(       // Port list
    input a,
    input b,
    output Sum,
    output Carry
    );
    
    // Design Circuit
    assign Sum = a ^ b;
    assign Carry = a & b;
endmodule

 

 

---

2.  Full Adder

 

• S = A⊕B⊕CIN (XOR Gate 2개)
• COUT = AB+CIN(A⊕B)

 

module FullAdder(
    input Cin,
    input a,
    input b,
    output Sum,
    output Carry
    );
    
    wire w_Sum1, w_Carry1, w_Carry2;

    HalfAdder u_HA1(
        .a(a),
        .b(b),
        .Sum(w_Sum1),
        .Carry(w_Carry1)
    );
    HalfAdder u_HA2(
        .a(w_Sum1),
        .b(Cin),
        .Sum(Sum),
        .Carry(w_Carry2)
    );
    
    assign Carry = w_Carry1 | w_Carry2;

endmodule

RTL Schematic

 

 

Simulation

module tb_FullAdder();

    reg a;
    reg b;
    reg Cin;
    wire Sum;
    wire Carry;
    
    FullAdder test_FA(
        .a(a),
        .b(b),
        .Cin(Cin),
        .Sum(Sum),
        .Carry(Carry)
    );
    
    initial begin
        #00 Cin = 0; a = 0; b = 0;
        #10 Cin = 0; a = 0; b = 1;
        #10 Cin = 0; a = 1; b = 0;
        #10 Cin = 0; a = 1; b = 1;
        #10 Cin = 1; a = 0; b = 0;
        #10 Cin = 1; a = 0; b = 1;
        #10 Cin = 1; a = 1; b = 0;
        #10 Cin = 1; a = 1; b = 1;
        #10 $finish;
     end

endmodule

 

 

---

3.  4bit Adder

 

module _4BitAdder(
    input a0,
    input a1,
    input a2,
    input a3,
    input b0,
    input b1,
    input b2,
    input b3,
    output Sum0,
    output Sum1,
    output Sum2,
    output Sum3,
    output Carry
    );
    
    wire w_Carry0, w_Carry1, w_Carry2;
    
    HalfAdder u_HA1(
        .a(a0),
        .b(b0),
        .Sum(Sum0),
        .Carry(w_Carry0)
    );
    FullAdder u_FA1(
        .a(a1),
        .b(b1),
        .Cin(w_Carry0),
        .Sum(Sum1),
        .Carry(w_Carry1)
    );
    FullAdder u_FA2(
        .a(a2),
        .b(b2),
        .Cin(w_Carry1),
        .Sum(Sum2),
        .Carry(w_Carry2)
    );
    FullAdder u_FA3(
        .a(a3),
        .b(b3),
        .Cin(w_Carry2),
        .Sum(Sum3),
        .Carry(Carry)
    );
    
endmodule

module FullAdder(
    input Cin,
    input a,
    input b,
    output Sum,
    output Carry
    );
    
    wire w_Sum1, w_Carry1, w_Carry2;

    HalfAdder u_HA1(
        .a(a),
        .b(b),
        .Sum(w_Sum1),
        .Carry(w_Carry1)
    );
    HalfAdder u_HA2(
        .a(w_Sum1),
        .b(Cin),
        .Sum(Sum),
        .Carry(w_Carry2)
    );
    
    assign Carry = w_Carry1 | w_Carry2;
endmodule

module HalfAdder(       // Port list
    input a,
    input b,
    output Sum,
    output Carry
    );
    
    // Design Circuit
    assign Sum = a ^ b;
    assign Carry = a & b;
endmodule

RTL Schematic

 

 

Simulation

module tb_4bitAdder();
    reg a0;
    reg a1;
    reg a2;
    reg a3;
    reg b0;
    reg b1;
    reg b2;
    reg b3;
    wire Sum0;
    wire Sum1;
    wire Sum2;
    wire Sum3;
    wire Carry;
    
    _4BitAdder test_banch(
        .a0(a0),
        .a1(a1),
        .a2(a2),
        .a3(a3),
        .b0(b0),
        .b1(b1),
        .b2(b2),
        .b3(b3),
        .Sum0(Sum0),
        .Sum1(Sum1),
        .Sum2(Sum2),
        .Sum3(Sum3),
        .Carry(Carry)
    );
    
    initial begin
        #00 a3 = 0; a2 = 0; a1 = 1; a0 = 0; b3 = 1; b2 = 1; b1 = 0; b0 = 1;
        #10 a3 = 1; a2 = 0; a1 = 1; a0 = 1; b3 = 1; b2 = 0; b1 = 0; b0 = 0;
        #10 a3 = 0; a2 = 1; a1 = 1; a0 = 1; b3 = 1; b2 = 1; b1 = 0; b0 = 1;
        #10 $finish;
    end

endmodule

 

 

 

 

 

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