[FullCustomIC] Cadence Virtuoso_4x1 MUX(Logic, Switch), 8x1 MUX(Logic, Switch), 16x1 MUX(Logic, Switch)

1.  4x1 MUX(Logic)

 

⦁ Truth Table

VINA	VINB	VINC	VIND	S0	S1	VOUT
A	B	C	D	0	0	A
A	B	C	D	1	0	B
A	B	C	D	0	1	C
A	B	C	D	1	1	D

 

(1) : Schematic  /   (2) : Symbol

(1) : test circuit  /  (2) : 4x1 MUX(Logic) Simulation

 

4x1 MUX(Logic) Layout

(1) : DRC  /   (2) : LVS

 

 

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2.  4x1 MUX(Switch)

 

(1) : Schematic  /  (2) : Symbol

(1) : test circuit  / (2) : Simulation

 

4x1 MUX(Switch) Layout

(1) : DRC  /  (2) : LVS

 

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3.  8x1 MUX(Logic)

 

⦁ Truth Table

S2	S1	S0	VOUT
0	0	0	VINA
0	0	1	VINB
0	1	0	VINC
0	1	1	VIND
1	0	0	VINE
1	0	1	VINF
1	1	0	VING
1	1	1	VINH

 

(1) : Schematic  /  (2) : Symbol

(1) : test circuit  / (2) : Simulation

 

8x1 MUX(Logic) Layout

(1) : DRC  /  (2) : LVS

 

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4.  8x1 MUX(Switch)

 

(1) : Schematic  /  (2) : Symbol

(1) : test circuit  / (2) : Simulation

 

8x1 MUX(Switch) Layout

(1) : DRC  /  (2) : LVS

 

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5.  16x1 MUX(Logic)

 

⦁ Truth Table

S3	S2	S1	S0	VOUT
0	0	0	0	VINA
0	0	0	1	VINB
0	0	1	0	VINC
0	0	1	1	VIND
0	1	0	0	VINE
0	1	0	1	VINF
0	1	1	0	VING
0	1	1	1	VINH
1	0	0	0	VINI
1	0	0	1	VINJ
1	0	1	0	VINK
1	0	1	1	VINL
1	1	0	0	VINM
1	1	0	1	VINN
1	1	1	0	VINO
1	1	1	1	VINP

 

(1) : Schematic  /  (2) : Symbol

(1) : test circuit  / (2) : Simulation

 

16x1 MUX(Logic) Layout

(1) : DRC  /  (2) : LVS

 

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6.  16x1 MUX(Switch)

 

(1) : Schematic  /  (2) : Symbol

(1) : test circuit  / (2) : Simulation

 

16x1 MUX(Logic) Layout

(1) : DRC  /  (2) : LVS

 

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■  Multiplexer Summary

 

Area	2x1 MUX	4x1 MUX	8x1 MUX	16x1 MUX
Logic (μm^2)	27.2012	100.7257	288.4656	800.0629
Switch (μm^2)	17.7876	52.486	133.416	335.3676
Ratio	1.529	1.919	2.1621	2.3856

Transistor	2x1 MUX	4x1 MUX	8x1 MUX	16x1 MUX
Logic (unit)	14	42	98	210
Switch (unit)	6	16	34	68

 

▶ Switch level design 면적이 훨씬 작은 것을 확인 할 수 있다.

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Made By Minseok KIM